Register arrangement for a microcomputer with a register and further storage media

ABSTRACT

There is provided a register system of a microcomputer having a register that includes at least one register bit and having an additional storage arrangement allocated to the register and on which the data content of the register is able to be intermediately stored. To reduce the computing time for saving the data content of the register, while keeping the silicon surface required for the register system as small as possible, the additional storage arrangement includes at least one shift register having at least two shift register cells, the content of an arbitrary shift register cell being transferable into a register bit, and, conversely, the content of a register bit being transferable into an arbitrary shift register cell.

FIELD OF THE INVENTION

The present invention relates to a register system of a microcomputerhaving a register including at least one register bit, and having anadditional storage arrangement that is allocated to the register, and onwhich the data content of the register can be intermediately stored.

BACKGROUND INFORMATION

A microcomputer may include a plurality of different registers toincrease the processing speed. Thus, for example, the microprocessor ofa microcomputer may include a data register and an address register inits execution unit. For floating-point calculation, the processor mayinclude a plurality of registers (arithmetic registers) in the floatingpoint unit (FPU), and for calculation with whole numbers it may includea plurality of such registers in the integer unit (IU). In addition, amicroprocessor may also include command registers.

Data is filed in the registers by applications that run on themicrocomputer. If an application using a register is interrupted by ahigher-priority application wishing to use the same register, theregister must be freed for the higher-priority application as quickly aspossible and without data loss. For this purpose, the data, filed in theregister, of the lower-priority application may be stored intermediatelyin an additional storage arrangement. The additional storage arrangementmay include, for example, a stack on which the data of the register aresaved. The higher-priority application may then file its data in theregister. After the termination of the higher-priority application, thedata saved on the stack may be loaded back into the register, and theinterrupted, lower-priority application may then be continued.

A plurality of applications having different priorities may be executedin nested fashion, so that the data of a plurality of interruptedapplications are filed on the stack temporarily. For example, inmicrocomputers used for real-time processing, lower-priorityapplications may be interrupted by higher-priority applications, and thedata of the lower-priority applications should be saved from theregister on a stack. Interrupts are used for the interruption of thelower-priority application.

However, the saving of the content of a register on a stack may requirea relatively large number of clock pulses of the CPU. After theinterruption of a lower-priority application during the saving of thedata content of the register on a stack, a delay may result before theregister is free, and before the higher-priority application may beprocessed and may execute its actual tasks.

To reduce or avoid this delay of a higher-priority application, theadditional storage arrangement may include register banks, i.e., tomultiply realize the registers of the microcomputer. When necessary, thedata from the register may be saved in a short time on the registerbanks, with a relatively small number of clock pulses. However, theregister banks are complete registers. Since the flip-flops require arelatively large surface, the-register banks correspondingly require alarge amount of silicon surface. However, for reasons of space and cost,a microprocessor should be implemented on a silicon surface that is assmall as possible, or as many registers as possible should be situatedon the same surface.

SUMMARY OF THE INVENTION

An object of an exemplary embodiment according to the present inventionis to construct and develop a register system so that the computing timefor saving data content of the register is reduced, while the siliconsurface required for the register system is kept as small as possible.

To achieve this object, based on the register system of the type namedabove, an exemplary embodiment according to the present inventionprovides the additional storage arrangement as at least one shiftregister having at least two shift register cells, the content of anarbitrary shift register cell being transferable into a register bit,and, conversely, the content of a register bit being transferable intoan arbitrary shift register cell.

In German Published Patent Application No. 196 11 520, an IDDQ test fora computer is referred to, in which a control unit contains anarrangement that causes the computer to assume particular operatingstates. In addition, an acquisition arrangement is provided thatacquires the current or the voltage of the power supply circuit of thecomputer, whereupon, in a comparator arrangement, the acquired currentor the acquired voltage is compared with at least one predeterminedthreshold value. For the actuation of the display device and/or of theswitching off, an actuating arrangement is provided that, depending onthe result of the comparison, displays an error if necessary, or, inreaction to such an error, causes the entire system or subareas of thesystem to switch off.

In an exemplary register system according to the present invention, theregister is therefore not multiply realized, but rather is merelyprovided with at least one additional shift register for the saving ofthe data content of the register. Moreover, since shift registersrequire a smaller silicon surface than do register banks that areequivalent in terms of storage space, an exemplary register systemaccording to the present invention may require a small silicon surface.

For the saving of the data content of the register in the shiftregister, a smaller number of clock pulses may be required, in which thecontent of the register is saved on a stack.

An exemplary register system according to the present inventiontherefore requires a low number of clock pulses of the CPU for thesaving of the data content of the register, while requiring only a smallsilicon surface.

If static structures (CMOS architecture) are used exclusively in anexemplary register system according to the present invention, then thefunctional capacity of the microcomputer may be tested with the aid ofan IDDQ test. The IDDQ test is based on the fact that error-free CMOScircuits have an extremely small power consumption when they are in anidle state. An error in the CMOS circuit may result in a significantincrease in the power consumption. It is understood that the IDDQ testis described in detail on the website of the Center for ElectronicDesign, Communications & Computing.

According to an exemplary embodiment of the present invention, a shiftregister is allocated to each register bit of the register. In thismanner, the content of an arbitrary register bit may be shifted into theshift register allocated to the register bit as needed. In this way, thesaving of the data content of the register to the shift register may besimplified and accelerated.

According to another exemplary embodiment of the present invention, eachshift register cell is a charge-coupled device (CCD) element. Forexample, each shift register cell may have a cell transfer gate, acharge storage unit, and an inverter. A shift register cell fashioned inthis way does not constitute a complete flip-flop, and thus requires acorrespondingly smaller amount of silicon surface. Nonetheless, thememory cells of the shift register according to an exemplary embodimentof the present invention may receive the content of a register bitrapidly and reliably, may store it intermediately at least for theduration of the loading of the register by a higher-priorityapplication, and, after termination of the higher-priority application,may transfer it rapidly and reliably back into the register bit.

The inverter may include two transistors connected in series. The celltransfer gate includes at least one transistor. The charge storage unitof an exemplary shift register cell according to the present inventionmay be a gate capacitor of the inverter. Alternatively, the chargestorage unit may be a separate capacitor. According to this exemplaryembodiment, the shift register cell thus has only three transistors. Incontrast, for example, it is believed that an SRAM storage cell has sixor four transistors. It is also believed that a DRAM cell has only onetransistor, but requires an extensive refresh logic unit.

According to another exemplary embodiment of the present invention, aninput transfer gate is situated between the register and the first shiftregister cell. According to yet another exemplary embodiment of thepresent invention, the last shift register cell is connected with thefirst shift register cell via an output transfer gate. By opening theoutput transfer gate, the content of the last shift register cell may beshifted into the first shift register cell, as long as its transfer gateis open. If the transfer gate of the first shift register cell is closedand the input transfer gate is open, the content of the last shiftregister cell may also be shifted directly into the register bit towhich the shift register is allocated.

The cell transfer gates are connected with a clock generator to shiftthe data contents of the shift register cells from one shift registercell to the next in the pulse of the clock generator. Likewise, theinput transfer gate and the output transfer gate are connected with aclock generator. By controlling, i.e., opening or closing the varioustransfer gates of the shift register in the pulse of the clockgenerator, the data contents of the register may be received, shiftedback and forth within the shift register, and transferred to theregister again. The clock generator may be clocked by the system clockof the microcomputer or a multiple thereof.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows an exemplary register system according to the presentinvention.

FIG. 2 shows further detail of a shift register cell of a shift registershown in FIG. 1.

DETAILED DESCRIPTION

FIG. 1 shows an exemplary register system according to the presentinvention. This exemplary embodiment has a register 1 including aplurality of register bits R1 to Rn. A shift register 2, having aplurality of shift register cells S1, S2 to Sm, is allocated to eachregister bit R1 to Rn.

The design of a shift register cell S1 to Sm is explained in more detailbelow with reference to FIG. 2, in which shift register cell S2 of shiftregister 2, allocated to first register bit R1, is shown in an enlargedview. The remaining shift register cells are constructedcorrespondingly. Shift register cell S2 is a charge-coupled device (CCD)element. Shift register cell S2 has a cell transfer gate 3, a chargestorage unit 4, and an inverter 5. Cell transfer gate 3 is a transistor.Inverter 5 has two transistors 6, 7, connected in series. Transistor 6is a pmos transistor, and transistor 7 is an nmos transistor. The sourceof transistor 6 is connected to supply voltage VDD, and the drain oftransistor 7 is connected to ground. Charge storage unit 4 is a gatecapacitor of inverter 5. Alternatively, it may be a separate capacitor.

An input transfer gate 8 is situated between register 1 and each offirst shift register cells S1 of shift register 2. Last shift registercells Sm of shift register 2 are each connected, via an output transfergate 9, with first shift register cell S1 of the respective shiftregister 2. Input transfer gate 8 is connected with a clock generator 13via an input timing circuit 10. Output transfer gate 9 is connected withthis clock generator 13 via an output timing circuit 11, and celltransfer gate 3 of shift register cells S1 to Sm is connected with thisclock generator 13 via a timing circuit 12. Clock generator 13 receivesthe timing pulse from a system clock 14 of the microcomputer. Through acorresponding controlling of transfer gates 3, 8, 9 via timing circuits10, 11, 12, the data contents of register 1 may be saved in shiftregister 2, the data filed there may be shifted back and forth, and thedata contents may then be transferred again from shift register 2 intoregister 1. The content of register bits R1 to Rn may thus be stored inan arbitrary shift register cell S1 to Sm of the shift register 2allocated to the respective register bit R1 to Rn, and, conversely, mayalso be transferred from an arbitrary shift register cell S1 to Sm backinto register bit R1 to Rn.

In a shift register 2, the shifting of the content from one shiftregister cell S1 to Sm to the next may lasts, e.g., 5 ns. If the datacontent of shift register cells S1 to Sm may be shifted only in onedirection, then, in a shift register 2 having, for example, ten shiftregister cells S1 to Sm, a maximum access time of 50 ns results to thedata content of a shift register cell S1 to Sm. A register file selectcircuit 15 determines which of the shift registers 2 is to be controlledby clock generator 13 at a particular timing pulse.

In each instance, first shift register cells S1 of shift register 2 forma first register bank. Likewise, second shift register cells S2 of shiftregister 2 form a second register bank, up to the last shift registercells Sm, which form an m-th register bank. However, the register banksconstructed from shift register cells S1 to Sm require a small siliconsurface because the individual shift register cells S1 to Sm are notfashioned as complete flip-flops, and have only three transistors 3, 6,7. In this way, the space requirement of an exemplary register systemaccording to the present invention may be reduced, and the manufacturingcosts may be kept low due to the required small silicon surface.

What is claimed is:
 1. A register system of a microcomputer, comprising:a register including at least one register bit; and an additionalstorage arrangement allocated to the register and operable tointermediately store a data content of the register, wherein theadditional storage arrangement includes at least one shift registerhaving at least two shift register cells, a content of a selected one ofthe shift register cells is movable into one of the register bits, and acontent of a selected one of the register bits is movable into one ofthe shift register cells.
 2. The register system of claim 1, wherein ashift register is allocated to each of the register bits of theregister.
 3. The register system of claim 1, wherein each of the shiftregister cells includes a charge-coupled device element.
 4. The registersystem of claim 3, wherein each of the shift register cells includes acell transfer gate, a charge storage unit, and an inverter.
 5. Theregister system of claim 4, wherein the cell transfer gate of each ofthe shift register cells includes at least one transistor.
 6. Theregister system of claim 4, wherein the charge storage unit of each ofthe shift register cells includes one of a gate capacitor of therespective inverter and a separate capacitor.
 7. The register system ofclaim 1, wherein an input transfer gate is situated between the registerand a first one of the shift register cells.
 8. The register system ofclaim 7, wherein a last one of the shift register cells is connected tothe first one of the shift register cells via an output transfer gate.9. The register system of claim 8, wherein the input transfer gate andthe output transfer gate are connected to a clock generator.